[elecena] 1:3 LVPECL clock buffer with programable divider | RGE | 24

[elecena] 1:3 LVPECL clock buffer with programable divider | RGE | 24 | -40 to 85 - zmiany ceny The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50-Ω transmission lines. The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings; see for details. The CDCP1803 is characterized for operation from –40°C to 85°C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference. 1:3 LVPECL clock buffer with programable divider | RGE | 24 | -40 to 85 - 4.02 USD https://elecena.pl/product/30547732/1-3-lvpecl-clock-buffer-with-programable-divider-rge-24-40-to-85 2026-07-31 1:3 LVPECL clock buffer with programable divider | RGE | 24 | -40 to 85 - 4.62 USD https://elecena.pl/product/30547732/1-3-lvpecl-clock-buffer-with-programable-divider-rge-24-40-to-85 2026-10-02