24-Bit, 250 kSPS Sigma Delta ADC with 20 µs Settling

The AD7176-2 is a fast settling, highly accurate, high resolution, multiplexed Σ-Δ analog-to-digital converter (ADC) for low bandwidth input signals. Its inputs can be configured as two fully differential or four pseudo differential inputs via the integrated crosspoint multiplexer. An integrated precision, 2.5 V, low drift (2 ppm/°C), band gap internal reference (with an output reference buffer) adds functionality and reduces the external component count.

The maximum channel scan data rate is 50 kSPS/channel (settling time of 20 µs), resulting in fully settled data with 17 noise free bits. User-selectable output data rates range from 5 SPS to 250 kSPS. The resolution increases at lower speeds.

The AD7176-2 offers three key digital filters. The fast settling sinc5 + sinc1 filter maximizes the channel scan rate. The sinc3 filter maximizes the resolution for single-channel, low speed applications. For 50 Hz and 60 Hz environments, the AD7176-2 specific filter minimizes the settling times or maximizes the rejection of the line frequency. These enhanced filters enable simultaneous 50 Hz and 60 Hz rejection with a 27 SPS output data rate (with a settling time of 36 ms).

System offset and gain errors can be corrected on a per channel basis. This per channel configurability extends to the output data rate used for each channel when using a sinc5 + sinc1 filter. All switching of the crosspoint multiplexer is controlled by the ADC and can be configured to automatically control an external multiplexer via the GPIO pins.

The specified operating temperature range is −40°C to +105°C. The AD7176-2 is housed in a 24-lead TSSOP package.

Applications

* Process control: PLC/DCS modules

- Temperature and pressure measurement

* Medical and scientific multichannel instrumentation

* Chromatography

* Fast and flexible output rate—5 SPS to 250 kSPS

* Fast settling time—20 µs

* Channel scan data rate of 50 kSPS/channel

* Performance specifications

* 17 noise free bits at 250 kSPS

* 20 noise free bits at 2.5 kSPS

* 22 noise free bits at 5 SPS

* INL ±2.5 ppm of FSR

* 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling

* User-configurable input channels

* 2 fully differential or 4 pseudo differential

* Crosspoint multiplexer

* On-chip 2.5 V reference (drift 2 ppm/°C)

* Internal oscillator, external crystal, or external clock

* See data sheet fo additional features