The CY74FCT16543T and CY74FCT162543T are 16-bit, high-speed, low power latched transceivers that are organized as two independent 8-bit D-type latched transceivers containing two sets of eight D-type latches with separate Latch Enable (LEAB\, LEAB\) and Output Enable (OEAB\, OEAB\) controls for each set to permit independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for example, the A-to-B input Enable (CEAB\) must be LOW in order to enter data from A or to take data from B as indicated in the truth table. With CAEB\ LOW, a LOW signal on the A-to-B Latch Enable (LEAB\) makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB\ signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB\ and OEAB\ both LOW, the three-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB\, LEAB\, and OEAB\ inputs flow-through pinout and small shrink packaging and in simplifying board design. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16543T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162543T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162543T is ideal for driving transmission lines. The CY74FCT162H543T is a 24-mA balanced output part that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.