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  <title>[elecena] Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop - zmiany ceny</title>
  <description>The AUP family is TIs premier solution to the industrys low-power needs in
		battery-powered portable applications. This family assures a low static- and dynamic-power
		consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in
		increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent
		signal integrity (see Excellent Signal Integrity).

This is a single positive-edge-triggered D-type flip-flop. When data at the data (D)
		input meets the setup time requirement, the data is transferred to the Q
		output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level
		and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
		data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the
		die as the package.

This device is fully specified for partial-power-down applications using
		Ioff. The Ioff circuitry disables the outputs when
		the device is powered down. This inhibits current backflow into the device which prevents damage to
		the device.</description>
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