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  <title>[elecena] High Speed CMOS Logic Dual Positive-Edge Trigger J-K Flip-Flops with Set and Reset - zmiany ceny</title>
  <description>The HC109 and HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.</description>
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