The HMC988LP3E is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32. It is a versatile device with additional functionality including adjustable output phase, adjustable delay in 60 steps of ~ 20 ps, a clock synchronization function, and a clock invert option. Housed in a compact 3 × 3 mm SMT QFN package, the clock divider offers a high level of functionality. The device works with 3.3V supply or may be connected to 5V supply and utilize the optional on-chip regulator. This on-chip regulator may be bypassed. Up to 8 addressable HMC988LP3E devices can be used together on the SPI bus. The HMC988LP3E is ideally suited for data converter applications with extremely low phase noise requirements. APPLICATIONS * Basestation Digital Pre-Distortion Paths (DPD) * High Performance Automated Test Equipment (ATE) * Backplane Clock Skew Management * Phase Coherence of Multiple Clock Paths * Clock Delay Management ton Improve Setup & Hold Time Margins * PCB Signal Flight Time Offset Circuits * Track and Hold Circuits for ADC/DACs * Programmable Clock Divide by 1/2/4/8/16/32 * Delay Adjustment in Multiples of 1/2 Clock Cycles or in 60 Steps of 20 ps (Typ.) * –170 dBc/Hz Noise Floor @ 100 MHz Output