<?xml version="1.0" encoding="UTF-8"?>
<!--Generated at Tue, 29 Sep 2026 12:56:00 +0200-->
<rss version="2.0">
 <channel>
  <title>[elecena] 2-Phase, D-CAP+™ Step-Down Controller for VR13 CPU VCORE and DDR Memory - zmiany ceny</title>
  <description>The TPS53626 device is a driverless, VR13 SVID compliant, synchronous buck
controller.		Advanced control features such as D-CAP+ architecture with
		overlapping pulse support undershoot reduction (USR) and overshoot reduction
(OSR) provide fast		transient response, lowest output capacitance and high
efficiency. The device also supports		single-phase operation in CCM or DCM for
light-load efficiency boost. The device integrates a full		set of VR13 I/O
features including VRREADY (PGOOD), ALERT and		 VRHOT.
The SVID interface address allows programming from 00h to 07h.		Adjustable
control of VOUT slew rate can be programmed as high as		20mV/uS.

Paired with the TI NexFET Power Stage, this total		solution delivers
exceptionally high speed and low switching loss. The TPS53626 also offers four
		default modes that configure VCCIO and VMCP settings with one single external
resistor to save		component count and board space.

The TPS53626 device package is a space saving, thermally enhanced 32-pin VQFN
package		that operates from –40°C to 105°C.

	 	 		 For all available
packages, see the		 orderable addendum at the end of the document.</description>
 </channel>
</rss>
