The AD7625 is a 16-bit, 6 MSPS, charge redistribution successive approximation register (SAR) based architecture analog-to-digital converter (ADC). SAR architecture allows unmatched performance both in noise (93 dB SNR) and in linearity (1 LSB). The AD7625 contains a high speed, 16-bit sampling ADC, an internal conversion clock, and an internal buffered reference. On the CNV± rising edge, it samples the voltage difference between the IN+ and IN− pins. The voltages on these pins swing in opposite phase between 0 V and REF. The 4.096 V reference voltage, REF, can be generated internally or applied externally. All converted results are available on a single LVDS self-clocked or echoed-clock serial interface, reducing external hardware connections. The AD7625 is housed in a 32-lead, 5 mm × 5 mm LFCSP with operation specified from −40°C to +85°C. APPLICATIONS * High dynamic range telecommunications * Receivers * Digital imaging systems * High speed data acquisition * Spectrum analysis * Test equipment * Throughput: 6 MSPS * SNR: 93 dB * INL: ±0.45 LSB typical, ±1 LSB maximum * DNL: ±0.3 LSB typical, ±0.5 LSB maximum * Power dissipation: 135 mW https://elecena.pl/product/908644/16-bit-6msps-pulsar-differential-adc 2009-10-07 https://elecena.pl/product/908644/16-bit-6msps-pulsar-differential-adc 2018-03-29 https://elecena.pl/product/908644/16-bit-6msps-pulsar-differential-adc 2025-01-20