ENC28J60-I/SP - 10Base-T Ethernet controller, SPI, EEE 802.3, DIP-28

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ENC28J60-I/SP - 10Base-T Ethernet controller, SPI, EEE 802.3, DIP-28 RSS 5.88 5.88 EUR27.63 PLN
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4.50 EUR

10Base-T Ethernet Controller with SPI Interface

Description: The ENC28J60 is a stand-alone Ethernet controller with an industry standard Serial Peripheral Interface (SPI). It is designed to serve as an Ethernet network interface for any controller equipped with SPI. The ENC28J60 meets all of the IEEE 802.3 specifications. It incorporates a number of packet filtering schemes to limit incoming packets. It also provides an internal DMA module for fast data throughput and hardware assisted checksum calculation, which is used in various network protocols. Communication with the host controller is implemented via an interrupt pin and the SPI, with clock rates of up to 20 MHz. Two dedicated pins are used for LED link and network activity indication.

Ethernet Controller Features: • Ethernet Controller Features • IEEE 802.3™ Compatible Ethernet Controller • Fully Compatible with 10/100/1000Base-T Networks • Integrated MAC and 10Base-T PHY • Supports One 10Base-T Port with Automatic Polarity Detection and Correction • Supports Full and Half-Duplex modes • Programmable Automatic Retransmit on Collision • Programmable Padding and CRC Generation • Programmable Automatic Rejection of Erroneous Packets • SPI Interface with Clock Speeds up to 20 MHz

Buffer: • 8-Kbyte Transmit/Receive Packet Dual Port SRAM • Configurable Transmit/Receive Buffer Size • Hardware Managed Circular Receive FIFO • Byte-Wide Random and Sequential Access with Auto-Increment • Internal DMA for Fast Data Movement • Hardware Assisted Checksum Calculation for Various Network Protocols

Medium Access Controller (MAC) Features • Supports Unicast, Multicast and Broadcast Packets • Programmable Receive Packet Filtering and Wake-up Host on Logical AND or OR of the Following: - Unicast destination address - Multicast address - Broadcast address - Magic Packet™ - Group destination addresses as defined by 64-bit Hash Table - Programmable Pattern Matching of up to 64 bytes at user-defined offset

Physical Layer (PHY) Features • Loopback mode • Two Programmable LED Outputs for LINK, TX, RX, Collision and Full/Half-Duplex Status

Operational • Six Interrupt Sources and One Interrupt Output Pin • 25 MHz Clock Input Requirement • Clock Out Pin with Programmable Prescaler • Operating Voltage of 3.1V to 3.6V (3.3V typical) • 5V Tolerant Inputs • Temperature Range: -40°C to +85°C Industrial, 0°C to +70°C Commercial (SSOP only) • 28-Pin SPDIP, SSOP, SOIC, QFN Packages

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