1:10 high speed clock buffer with selectable input clock driver

The CDCLVP111-SP clock driver distributes one

differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential

LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The

CDCLVP111-SP can accept two clock sources into an input multiplexer. The

CDCLVP111-SP is specifically designed for driving 50Ω transmission lines. When an

output pin is not used, leaving the pin open is recommended to reduce power

consumption. If only one of the output pins from a differential pair is used, the

other output pin must be identically terminated to 50Ω.

The VBB reference voltage output is

used if single-ended input operation is required. In this case, the VBB

pin must be connected to CLK0 and bypassed to GND using a 10nF

capacitor.

For high-speed performance, the differential mode is strongly recommended.

The CDCLVP111-SP is characterized for operation from –55°C to 125°C.