12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter

The AD9434 is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. The VREF pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the SPI port).

The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.

Fabricated on an advanced BiCMOS process, the AD9434 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C). This part is protected under a U.S. patent.

APPLICATIONS

* Wireless and wired broadband communications

* Cable reverse path

* Communications test equipment

* Radar and satellite subsystems

* Power amplifier linearization

PRODUCT HIGHLIGHTS

* High Performance.

Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input.

* Low Power.

Consumes only 660 mW at 500 MSPS.

* Ease of Use.

LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample and hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.

* Serial Port Control.

Standard serial port interface supports various product functions, such as data formatting, power-down, gain adjust, and output test pattern generation.

* The AD9434 is pin compatible with the AD9230, and can be substituted in many applications with minimal design changes.

* SNR = 65 dBFS at fIN up to 250 MHz at 500 MSPS

* ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)

* SFDR = −78 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)

* Integrated input buffer

* Excellent linearity

* DNL = ±0.5 LSB typical

* INL = ±0.6 LSB typical

* LVDS at 500 MSPS (ANSI-644 levels)

* 1 GHz full power analog bandwidth

* On-chip reference, no external decoupling required