Highly Integrated 32-Bit Floating-Point SHARC Processor for Home Theater

The third generation of SHARC Processors, which includes the ADSP-21262, ADSP-21266, ADSP-21364, and ADSP-21365, offers increased performance, audio-centric peripherals, and new memory configurations, including on-chip ROM, that are capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible and completely code-compatible with all prior SHARC Processors. These newest members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-perfomance audio applications.

Third generation SHARC Processors also integrate audio-specific peripherals designed to simplify hardware design and reduce time to market. Grouped together, and broadly named the Digital Audio Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, an Input Data Port (IDP), Precision Clock Generators (PCG), and timers. This flexibility of resource utilization combined with the ease of use of the SHARC Processor programming model allow manufacturers to leverage a single hardware design for multiple products with varying I/O requirements.

SHARC Melody Platform for the Home

The SHARC Melody platform combines high-performance processors with optimized software, thus offering complete audio solutions to Home Theater manufacturers. The ADSP-21266 is a large memory, high-performance device targeted primarily at mid- to high-end home theater systems. SHARC Melody solutions are offered through on-chip ROM containing industry standard audio decoder algorithms such as

* PCM

* Dolby Digital*

* Dolby Digital EX2*

* Dolby Pro Logic IIx*

* DTS 5.1*

* DTS ES*

* DTS Neo:6 (Cinema and music)*

* DTS 96/24*

* MPEG2 AAC LC

* MPEG2 (BC) 2 channel

These algorithms are factory mask-programmed ensuring that single-chip system implementations are realized and system bill of materials costs are minimized.

* License agreement required from IP holders prior to receipt of silicon samples.

* 200MHz /1.2 GFLOPs SIMD SHARC core supporting IEEE 32-bit floating-point, 40-bit floating-point and 32-bit fixed-point data types

* 2Mbits SRAM; On-chip ROM embedded with industry-standard audio decode and post-processing algorithms available to qualified Dolby and DTS licensees only.

* 16-bit parallel port

* Digital Audio Interface (DAI) enabling user-definable access to peripherals including precision clock generators (PCG), input data port (IDP), and general purpose I/O

* 22 zero-overhead DMA channels

* 6 serial ports (SPORTs) supporting I2S, left-justified sample pair, and TDM modes

* SPI-compatible port supporting master and slave modes

* 3 full-featured timers

* PLL capable of a variety of multiplier ratios

* 136-ball MiniBGA and 144-lead LQFP packages

* Commercial and Industrial temperature ranges