3-Channel Clock Generator, 24 Outputs

The AD9531 provides a multioutput clock generator function and three on-chip phase-locked loop (PLL) cores with SPI programmable output frequencies and formats.

PLL1 provides two reference inputs and 10 outputs and includes four user selectable loop configurations. The PLL has a fully integrated loop filter requiring only a single external capacitor (or a series RC network). PLL1 provides a wide range of output frequencies up to 400 MHz and is capable of operating with an external voltage controlled crystal oscillator (VCXO) and loop filter, instead of the integrated voltage controlled oscillator (VCO) and loop filter.

PLL2 is an integer-N PLL providing a single reference input and 12 outputs. PLL2 synthesizes output frequencies up to 400 MHz from the REF2x source and synchronizes the output clocks to the input reference.

PLL3 provides a single reference input and two outputs. PLL3 synthesizes output frequencies up to 400 MHz from the REF3x source and synchronizes the output clocks to input reference.

The AD9531 is available in an 88-lead LFCSP and is specified over the −40°C to +85°C operating temperature range.

Throughout this data sheet, multifunction pins, such as LOR/M4, are referred to either by the entire pin name or by a single function of the pin (for example, LOR, when only that function is relevant). In other cases, the text and figures of this data sheet contain references to a channel rather than a pin. For example, REFA refers to the REFA channel rather than the REFAP and REFAN pins. Likewise, OUT31 refers to Channel 1 of PLL3 rather than the OUT31P and OUT31N pins. Additionally, an abbreviated notation for a pin pair replaces an explicit reference to a each pin (for example, REFAx signifies the REFAN and REFAP pins.).

Applications

* Radio equipment controller clocking

* Low jitter/phase noise clock generation and distribution

* Clock generation and translation for SONET, 10GE, 10G FC, and other 10 Gbps protocols

* 40 Gbps/100 Gbps networking line cards, including SONET, synchronous ethernet, OTU2/3/4

* Forward error correction (G.710)

* High performance wireless transceivers

* ATE and high performance instrumentation

* Broadband infrastructures

* Ethernet line cards, switches, and routers

* SATA and PCI-express

* 3 fully integrated PLL/VCO cores (PLL1, PLL2, and PLL3)

* Jitter performance: 0.462 ps rms typical PLL1, fractional-N mode, 12 kHz to 20 MHz bandwidth

* Loss of reference and lock detection for each PLL

* Pin-configurable common frequency translations

* Automatic synchronization of all outputs on power-up

* Manual output synchronization capability

* Package available in an 88-lead LFCSP

* PLL1 details

* Fractional-N/integer-N modes

* Optional external VCXO

* PLL2 details

* Integer-N mode (1 reference clock input

* Input format: differential/single-ended/crystal

* PLL3 details

* Integer-N mode (1 reference clock input)

* Frequency range: 9.5 MHz to 100 MHz

* See data sheet for additional features