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3.3 Volt Phase-Lock Loop Clock Driver

Intersil

The 2510C is a high-performance, low-skew, low-jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The 2510C operates at 3.3V VCC and drives up to ten clock loads.

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