Clock Slicer User Configurable PECL Output ZDB

The 527-03 is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The 527-03 aligns rising edges on CLKIN with FBPECL at a ratio determined by the reference and feedback dividers. For a PECL input and output clock with zero delay, use the 527-04.