8K x 36 x 2 Triple-Bus FIFO, 5.0V

The 723676 is a 8K x 36 x 2 Triple Bus sync FIFO memory has two independent dual-port SRAM FIFOs on board each chip that can buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. FIFO data can be read and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. Communication between each port may bypass the FIFOs via two mailbox registers. This device can operate in the IDT Standard mode or the first word fall through mode.