1.65V-to-5V eight-channel shift register with logic-level shifter

The SN74LV8T594 device contains an

8-bit, serial-in, parallel-out shift register.

Each parallel output of the shift register is fed

through a storage register before reaching the

primary device outputs (QA through

QH). Separate clocks (SRCLK and RCLK)

and direct overriding clear

(SRCLR and

RCLR) inputs are provided for

both the shift and storage registers, allowing for

loading data separately from sending it to the

outputs. Additionally, the last output of the

internal shift register is sent directly to the

output QH’ providing a method to

daisy-chain multiple shift registers.

The input is designed with a reduced threshold

circuit to support up translation when the supply

voltage is larger than the input voltage.

Additionally, the 5V tolerant input pins enable

down translation when the input voltage is larger

than the supply voltage. The output level is

always referenced to the supply voltage

(VCC) and supports 1.8V, 2.5V, 3.3V,

and 5V CMOS levels.