Enhanced-product 8-bit shift register with logic-level shifter

The SN74LV8T164-EP device

contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear

(CLR) input. The gated serial (A and B) inputs permit complete

control over incoming data; a low at either input inhibits entry of the new data and resets

the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input

enables the other input, which then determines the state of the first flip-flop. Data at the

serial inputs is changeable while CLK is high or low, provided the minimum set-up time

requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

The input is designed with a reduced

threshold circuit to support up translation when the supply voltage is larger than the input

voltage. Additionally, the 5V tolerant input pins enable down translation when the input

voltage is larger than the supply voltage. The output level is always referenced to the

supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.