8-bit shift register with Schmitt-trigger inputs and 3-state output registers

The SN74HCS595 device contains an 8-bit, serial-in, parallel-out shift

register that feeds an 8-bit D-type storage register. All inputs include Schmitt-trigger

architecture, eliminating any erroneous data outputs due to slow-edged or noisy

input signals. The storage register has parallel 3-state outputs. Separate clocks

are provided for both the shift and storage register. The shift register has a

direct overriding clear (SRCLR) input, serial (SER) input, and

a serial output (QH’) for cascading. When the output-enable

(OE) input is high, the storage register outputs are in a

high-impedance state. Internal register data and serial output (QH’) are

not impacted by the operation of the OE input.