8-bit parallel-out serial shift registers

The SN74HCS264 device contains an 8-bit shift register

with AND-gated serial inputs and an asynchronous clear

(CLR) input. Data at the serial inputs

can be changed while CLK is high or low, provided the minimum setup

time requirements are met. All inputs include Schmitt-trigger

architecture, adding noise margin and eliminating any input

transition rate requirement. Clocking occurs on the

low-to-high-level transition of CLK.

Upon a clock trigger, the device will store the result of the (A ● B) input data line in the first register and propagate each register’s data to the next register. The outputs are inverted from the data stored.