Low Skew, 2:1 LVPECL MUX With 1:8 Fanout And Internal Termination

The 8S89200I is a high-speed 1-to-8 differential-to-LVDS clock divider that is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential inputs and VREFAC pins allow other differential signal families such as LVPECL, LVDS, and CML to be easily interfaced to the input with minimal use of external components.

The device also has a selectable ÷1, ÷2, ÷4 output divider, which can allow the part to support multiple output frequencies from the same reference clock. The 8S89200I is packaged in a small 5mm x 5mm 32-pin VFQFN package which makes it ideal for use in space-constrained applications.