Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW

The LMK5C33216

is a high-performance network clock generator, synchronizer, and jitter attenuator with

advanced reference clock selection and hitless switching capabilities designed to meet the

stringent requirements of communications infrastructure applications.

The LMK5C33216

integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing

flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input.

The APLL reference determines the long term frequency accuracy.

The 3 APLLs may operate independent of their

paired DPLL and be cascaded from another APLL to provide programmable frequency translation.

APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW)

VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the

jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for

additional frequency domains.

The device is fully programmable through

I2C or SPI interface. The onboard EEPROM can be used to customize system

start-up clocks.