4-output clock buffer for PCIe® Gen 1 to Gen 7

The CDCDB400 is a 4-output

LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock

for PCIe Gen 1-7, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC,

SRNS, or SRIS architectures. The SMBus interface and four output enable pins allow

the configuration and control of all four outputs individually. The CDCDB400 is a DB800ZL derivative buffer and meets or exceeds the

system parameters in the DB800ZL specification. The device also meets or exceeds the

parameters in the DB2000Q specification. The CDCDB400 is packaged

in a 5mm × 5mm, 32-pin VQFN package.