CMOS 8-Bit Addressable Latch

The CD4099BMS 8-bit addressable latch is a serial input, parallel output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic 0 level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1 of 8 demultiplexer; the bit that is addressed has an active output that follows the data input, while all unaddressed bits are held to a logic 0 level. The CD4099BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4X, Frit Seal DIP H1F, Ceramic Flatpack H6W.