4:1 Differential-to-LVDS Clock Multiplexer

The 854S054I is a 4:1 differential-to-LVDS clock multiplexer that can operate up to 2.5GHz. The 854S054I has four selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pull-down resistors. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).