Automotive octal D-type flip-flops with clear, integrated level translation

The SN74LV8T273-Q1 contains eight positive-edge-triggered D-type flip-flops with a

direct active low clear (CLR) input.

Information at the data (D) inputs

meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a

particular voltage level and is not directly related to the transition time of the

positive-going pulse. When CLK is at either the high or low level, the D input has

no effect at the output.

The input is designed with a reduced

threshold circuit to support up translation when the supply voltage is larger than

the input voltage. Additionally, the 5V tolerant input pins enable down translation

when the input voltage is larger than the supply voltage. The output level is always

referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and

5V CMOS levels.