Eight-bit fixed-direction level translator with tri-state outputs and level-shifting inputs

The input is designed with a reduced

threshold circuit to support up translation when the supply voltage is larger than

the input voltage. Additionally, the 5V tolerant input pins enable down translation

when the input voltage is larger than the supply voltage. The output level is always

referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and

5V CMOS levels.