12.8GHz Buffer/Multiplier/Divider with SYSREF and FPGA Clock - Enhanced Product

The high frequency capability,

extremely low jitter and programmable clock input and output delay of this device,

makes a great approach to clock high precision, high-frequency data converters

without degradation of signal-to-noise ratio. Each of the four high frequency clock

outputs and additional LOGICLK outputs with larger divider range, is paired with a

SYSREF output clock signal. The SYSREF signal for JESD204B/C interfaces can either

be internally generated or passed in as an input and re-clocked to the device

clocks. The noiseless delay adjustment at input path of the high frequency clock

input and individual clock output paths insures low skew clocks in multi-channel

system. For data converter clocking application, having the jitter of the clock less

than the aperture jitter of the data converter is important. In applications where

more than four data converters need to be clocked, a variety of cascading

architectures can be developed using multiple devices to distribute all the high

frequency clocks and SYSREF signals required. This device, combined with an

ultra-low noise reference clock source, is an exemplary choice for clocking data

converters, especially when sampling above 3GHz.