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CY7C25682KV18-550BZXC

Infineon

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CY7C25682KV18-550BZXC
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Infineon
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CY7C25682KV18-550BZXC is a 72-Mbit DDR II+ synchronous pipelined SRAM organized as 4M × 18 with a two-word burst architecture. It runs up to 550 MHz clock (1100 MHz DDR transfer) with 2.5-cycle read latency, using K/K input clocks for DDR timing. It operates from 1.7 V to 1.9 V VDD and 1.4 V to VDD VDDQ, and integrates ODT, CQ/CQ echo clocks, QVLD data-valid, PLL, and IEEE 1149.1 JTAG.

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