CY7C1471BV25-133AXI

CY7C1471BV25-133AXI is a 72-Mbit (2 M × 36) synchronous flow-through burst SRAM with No Bus Latency (NoBL) architecture for true back-to-back reads and writes with no wait states. It supports 133 MHz operation with 6.5 ns clock-to-data valid and registered inputs. Features include byte write, linear or interleaved 4-beat bursts, three chip enables plus OE for depth expansion, and ZZ sleep mode with data retention.