SoC with Octal Arm® Cortex®-A72, 24 TOPS of AI, C7xDSP, and GPU for vision perception and analytics | ALY | 1414 | -40 to 125

The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1

processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV)

applications and built on extensive market knowledge accumulated over a decade of

TI’s leadership in the ADAS processor market. The unique combination

high-performance compute, deep-learning engine, dedicated accelerators for signal

and image processing in an functional safety compliant targeted architecture make

the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 devices a great fit for several imaging,

vision, radar, sensor fusion and AI applications such as: Robotics, Mobile

machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways,

Retail automation, Medical Imaging, and so on. The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1

TDA4AP-Q1 provides high performance compute for both traditional and deep learning

algorithms at industry leading power/performance ratios with a high level of system

integration to enable scalability and lower costs for advanced automotive platforms

supporting multiple sensor modalities in centralized ECUs or stand-alone sensors.

Key cores include next generation DSP with scalar and vector cores, dedicated deep

learning and traditional algorithm accelerators, latest Arm and GPU processors for

general compute, an integrated next generation imaging subsystem (ISP), video codec,

Ethernet hub and isolated MCU island. All protected by automotive grade safety and

security hardware accelerators.

Key Performance Cores

Overview

The next generation C7™ DSP combines TI’s industry

leading DSP and EVE cores into a single higher performance core and adds floating

point vector calculation capabilities, enabling backward compatibility for legacy

code while simplifying software programming. A single instance of the new “MMAv2”

deep learning accelerator enables performance up to 8 TOPS within the lowest power

envelope in the industry when operating at the typical automotive worst case

junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide

vision pre-processing plus distance and motion processing with no impact on system

performance.

General Compute Cores and

Integration Overview

Separate eight core cluster configuration of Arm

Cortex-A72 facilitates multi-OS applications with minimal need

for a software hypervisor. Eight Arm® Cortex®-R5F subsystems enable low-level,

timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for

applications. The integrated IMG BXS-4-64 GPU offers up to 50 GFLOPS to enable

dynamic 3D rendering for enhanced viewing applications. Building on the existing

world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader

sensor suite, support for higher bit depth, and features targeting analytics

applications. Integrated diagnostics and safety features support operations up to

ASIL-D/SIL-3 levels while the integrated security features protect data against

modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and

Gigabit Ethernet switch are included along with CSI-2 ports to support throughput

for many sensor inputs. To further the integration, the TDA4VH-Q1 TDA4AH-Q1

TDA4VP-Q1 TDA4AP-Q1 family also includes an MCU island eliminating the need for an

external system microcontroller.