Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer

The CDCLVD1204 clock

buffer distributes one of two selectable clock inputs (IN0

and IN1) to 4 pairs of differential LVDS clock outputs (OUT0

through OUT3) with minimum skew for clock distribution. The

CDCLVD1204 can accept two clock sources into an input

multiplexer. The inputs can either be LVDS, LVPECL, or

LVCMOS.

The CDCLVD1204 is

specifically designed for driving 50Ω transmission lines. In

case of driving the inputs in single ended mode, the

appropriate bias voltage, VACREF, must be

applied to the unused negative input pin.

The INSEL pin

selects the input which is routed to the outputs. If this

pin is left open, it disables the outputs (static). The part

supports a fail safe function. The device incorporates an

input hysteresis which prevents random oscillation of the

outputs in the absence of an input signal.

The device operates

in 2.5V supply environment and is characterized from –40°C

to 85°C (ambient temperature). The CDCLVD1204 is packaged in

small, 16-pin, 3mm × 3mm VQFN package.