1-To-8 TTL clock driver with 3-state outputs

The CDC339 is a high-performance,

low-skew clock driver. It is specifically designed for applications requiring

synchronized output signals at both the primary clock frequency and one-half the

primary clock frequency. The four Y outputs switch in phase and at the same

frequency as the clock (CLK) input. The four Q outputs switch at one-half the

frequency of CLK.

When the output-enable

(OE) input is low and the clear (CLR)

input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high

transitions of CLK. Taking CLR low asynchronously resets the Q

outputs to the low level. When OE is high, the outputs are in

the high-impedance state.

The CDC339 is characterized for

operation from −40°C to 85°C.