3.3-V phase-lock loop clock driver with 9 outputs for DRAM applications

The CDCVF2509 is a high-performance,

low-skew, low-jitter, phase-lock loop (PLL) clock driver. The device uses a PLL to

precisely align, in both frequency and phase, the feedback (FBOUT) output to the

clock (CLK) input signal. The device is specifically designed for use with

synchronous DRAMs. The CDCVF2509 operates at a 3.3V VCCand provides

integrated series-damping resistors designed for driving point-to-point loads.

One bank of five outputs and one bank

of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty

cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of

outputs is enabled or disabled separately through the control (1G and 2G) inputs.

When the G inputs are high, the outputs switch in phase and frequency with CLK. When

the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs,

the CDCVF2509 does not require external RC networks. The loop filter for the PLL is

included on-chip, minimizing component count, board space, and cost.

The device is based on PLL circuitry,

therefore the CDCVF2509 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required

following power up and application of a fixed-frequency, fixed-phase signal at CLK,

and following any changes to the PLL reference or feedback signals. The PLL can be

bypassed by strapping AVCC to ground.

The CDCVF2509A is characterized for

operation from 0°C to 85°C.

For application information, see the

High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 and Using CDC2509A/2510A PLL with Spread

Spectrum Clocking (SSC) application notes.