Single UART with 16-Byte FIFOs and Auto Flow Control

The TL16C550C and the TL16C550CI are

functional upgrades of the TL16C550B asynchronous communications element (ACE),

which in turn is a functional upgrade of the TL16C450. Functionally equivalent to

the TL16C450 on power up (character or TL16C450 mode), the TL16C550C and the

TL16C550CI, like the TL16C550B, can be placed in an alternate FIFO mode. This

relieves the CPU of excessive software overhead by buffering received and

transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes

including three additional bits of error status per byte for the receiver FIFO. In

the FIFO mode, there is a selectable autoflow control feature that can significantly

reduce software overload and increase system efficiency by automatically controlling

serial data flow using RTS output and CTS

input signals.

The TL16C550C and TL16C550CI perform serial-to-parallel conversions on data received

from a peripheral device or modem and parallel-to-serial conversion on data received

from its CPU. The CPU can read the ACE status at any time. The ACE includes complete

modem control capability and a processor interrupt system that can be tailored to

minimize software management of the communications link.

Both the TL16C550C and the TL16C550CI ACE include a programmable baud rate generator

capable of dividing a reference clock by divisors from 1 to 65535 and producing a

16× reference clock for the internal transmitter logic. Provisions are included to

use this 16× clock for the receiver logic. The ACE accommodates a 1-Mbaud serial

rate (16-MHz input clock) so that a bit time is 1 µs and a typical character time is

10 µs (start bit, 8 data bits, stop bit).

Two of the TL16C450 terminal functions on the TL16C550C and the TL16C550CI have been

changed to TXRDY and RXRDY, which provide

signaling to a DMA controller.