Octal D-type Flip-Flops With Clear

These devices are

positive-edge-triggered D-type flip-flops with a

direct clear ( CLR) input.

Information at the data (D) inputs

meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a

particular voltage level and is not directly related to the transition time of the

positive-going pulse. When CLK is at either the high or low level, the D input has

no effect at the output.