Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

The ’HCT74 devices contain two independent

D-type positive-edge-triggered flip-flops. A low

level at the preset ( PRE) or

clear ( CLR) inputs sets or

resets the outputs, regardless of the levels of

the other inputs. When PRE

and CLR are inactive (high),

data at the data (D) input meeting the setup time

requirements are transferred to the outputs on the

positive-going edge of the clock (CLK) pulse.

Clock triggering occurs at a voltage level and is

not directly related to the rise time of CLK.

Following the hold-time interval, data at the D

input may be changed without affecting the levels

at the outputs.