High Speed CMOS Logic Quad 2-Input Multiplexers with Inverting 3-State Outputs

These devices are designed to multiplex signals from 4-bit data sources to 4-output data lines in bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (G)\ input is at a high logic level.

To ensure the high-impedance state during power up or power down, G\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.