Dual-Channel, 12-Bit, 80-MSPS Analog-to-Digital Converter (ADC)

The ADC322x are a high-linearity,

ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital

converter (ADC) family. The devices are designed specifically to support demanding,

high input frequency signals with large dynamic range requirements. An input clock

divider allows more flexibility for system clock architecture design and the SYSREF

input enables complete system synchronization. The ADC322x family supports serial

low-voltage differential signaling (LVDS) in order to reduce the number of interface

lines, thus allowing for high system integration density. The serial LVDS interface

is two-wire, where each ADC data are serialized and output over two LVDS pairs.

Optionally, a one-wire serial LVDS interface is available. An internal phase-locked

loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that

is used to serialize the 12-bit output data from each channel. In addition to the

serial data streams, the frame and bit clocks are also transmitted as LVDS

outputs.