Quad ADC (2V Input)

The ADAU1978 incorporates four high performance, analog-to-digital converters (ADCs) with 2 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta (Σ-Δ) architecture with continuous time front end for low EMI. An I2C/serial peripheral interface (SPI) control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1978 uses only a single 3.3 V supply. The part internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The ADAU1978 is available in a 40-lead LFCSP package. The on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with the frame clock, it eliminates the need for a separate high frequency master clock in the system.

Note that throughout this data sheet, multifunction pins, such as SCL/CCLK, are referred to either by the entire pin name or by a single function of the pin, for example, CCLK, when only that function is relevant.

Applications

* Automotive audio systems

* Active noise cancellation system

* Four 2V rms Differential Inputs

* On-chip phase-locked loop (PLL) for master clock

* Low electromagnetic interference (EMI) design

* 106 dB analog-to-digital converter (ADC) dynamic range

* Total harmonic distortion + noise (THD + N): −95 dB

* Selectable digital high-pass filter

* 24 bit stereo ADC with 8 kHz to 192 kHz sample rates