Sample

Serial-in shift registers | D | 14 | 0 to 70

... an asynchronous clear. The gated serial inputs (A ...

Sample

Automotive 3-to-8 line decoder demultiplexer with address latches | D | 16 | -40 to 125

... When the outputs are gated by either strobe input ...

Sample

High Speed CMOS Logic 4-Bit Binary Counter with Asynchronous Reset | N | 16 | -55 to 125

... count. The TE input is gated with the Q outputs of ...

Sample

Automotive Catalog 8-Bit Parallel-Load Shift Registers | PW | 16 | -40 to 125

... -out register features gated clock (CLK, CLK ...

Sample

Serial-out shift registers | D | 16 | 0 to 70

... chip. They feature gated clock inputs and ...

Sample

High Speed CMOS Logic 4-Bit Binary Counter with Synchronous Reset | N | 16 | -55 to 125

... count. The TE input is gated with the Q outputs of ...

Sample

8-Bit Parallel-Out Serial Shift Registers | D | 14 | -40 to 125

... clear (CLR) input. The gated serial (A and B ...

7472

7472 AND Gated JK Master/Slave Flip-Flop

Sample

High Speed CMOS Logic 4-Bit Binary Counter with Synchronous Reset | N | 16 | -55 to 125

... count. The TE input is gated with the Q outputs of ...

Sample

High Speed CMOS Logic 4-Bit Binary Counter with Asynchronous Reset | N | 16 | -55 to 125

... count. The TE input is gated with the Q outputs of ...

2.00

CD4096 Gated J-K Master-Slave Flip-Flops DIP14

Sample

CMOS Presettable Binary Up/Down Counter | N | 16 | -55 to 125

... , the CARRY-OUT must be gated with the clock, and ...

Sample

CMOS Presettable Binary Up/Down Counter (Dual Clock with Reset) | N | 16 | -55 to 125

... of 4 synchronously clocked, gated "D" type flip ...

Sample

CMOS Presettable BCD Up/Down Counter (Dual Clock with Reset) | N | 16 | -55 to 125

... of 4 synchronously clocked, gated "D" type flip ...

Sample

Automotive low-power fault protected CAN FD transceiver with WAKE and sleep mode | D | 14 | -40 to 150

... in which power is gated to all system components ...