Sample

Up to 1GHz Dual-SHARC+ DSP with 2x 640KB L1, 2048KB Shared L2 SRAM, 400-Ball FCBGA

... SRAM memory (with parity) increases low latency ...

Sample

Up to 1 GHz Dual-SHARC+ DSP with 2x 640KB L1, 2048KB Shared L2 SRAM

... SRAM memory (with parity) increases low latency ...

Sample

Arm Cortex-M33-based Microcontroller with 8KB Cache

... on-chip RAM with Parity or ECC, renewed security ...

Sample

Up to 800 MHz SHARC+ DSP w/ Integrated Arm Cortex-A5

... SRAM memory (with parity) increases low latency ...

1.8V Configurable Buffer with Address-Parity Test

28-Bit 1:2 Registered Buffer with Parity

1.8V Configurable Buffer with Address-Parity Test

28-Bit 1:2 Registered Buffer with Parity

OCTAL TRANSCEIVR W/PARITY

8-BIT TRANSCEIVER W/PARITY - CMOS VOH LEVELS

16 BIT BIDIRECTIOANL BUFFER/LATCH/REGISTER W/PARITY GENERATOR

Sample

1 GHz SHARC+ DSP w/ Integrated Arm Cortex-A55

... kB L1 instruction cache with parity/32 kB L1 data ...

Sample

Up to 1 GHz Dual-SHARC+ DSP w/ Integrated Arm Cortex-A55

... kB L1 instruction cache with parity/32 kB L1 data ...

10-Port SAS Expander at 1.5Gbps and 3.0Gbps

... , data path parity errors, disparity errors ...

12-PHY Serial Attached SCSI Edge Expander at 1.5Gbps and 3.0Gbps

... , data path parity errors, disparity errors ...