Sample

CMOS Dual 4-Bit Latch

... locks the data into the latch. A high on the reset ...

Sample

CMOS Dual 4-Bit Latch

... locks the data into the latch. A high on the reset ...

Sample

CMOS 8-Bit Addressable Latch

... addressable latch is ... low level, the latch acts as ...

Sample

CMOS 8-Bit Addressable Latch

... addressable latch is ... low level, the latch acts as ...

Sample

High Speed CMOS Logic 8-Bit Addressable Latch

Sample

High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch

... is HIGH data enters the latch and appears at the Q ...

Sample

High Speed CMOS Logic 8-Bit Addressable Latch

Sample

High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch

... is HIGH data enters the latch and appears at the Q ...

Sample

High Speed CMOS Logic 8-Bit Addressable Latch

Sample

High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latches

... is HIGH data enters the latch and appears at the Q ...

Sample

High Speed CMOS Logic 8-Bit Addressable Latch

Sample

High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch

... is HIGH data enters the latch and appears at the Q ...

Sample

8-Bit Addressable Latches

... table. In the addressable-latch mode, data at the ...

Sample

4-By-4 Register Files With 3-State Outputs

... is transferred to the latch output. When the write ...

Sample

4-Bit Bistable Latches

... outputs from a 4-bit latch, and are available in ...