Sample

CMOS Quad Clocked 'D' Latch

... types contain four latch circuits, each strobed ...

Sample

CMOS Quad NOR R/S Latch with 3-State Outputs

... ENABLE input connects the latch states to the Q ...

Sample

CMOS Quad NOR R/S Latch with 3-State Outputs

... ENABLE input connects the latch states to the Q ...

Sample

CMOS Quad NAND R/S Latch with 3-State Outputs

... ENABLE input connects the latch states to the Q ...

Sample

CMOS Quad NAND R/S Latch with 3-State Outputs

... ENABLE input connects the latch states to the Q ...

Sample

CMOS 8-Bit Addressable Latch

... addressable latch is ... low level, the latch acts as ...

Sample

CMOS 8-Bit Addressable Latch

... addressable latch is ... low level, the latch acts as ...

Sample

CMOS Dual 4-Bit Latch

... locks the data into the latch. A high on the reset ...

Sample

CMOS Dual 4-Bit Latch

... locks the data into the latch. A high on the reset ...

Sample

CMOS 8-Bit Addressable Latch

... addressable latch is ... low level, the latch acts as ...

Sample

CMOS 8-Bit Addressable Latch

... addressable latch is ... low level, the latch acts as ...

Sample

High Speed CMOS Logic 8-Bit Addressable Latch

Sample

High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch

... is HIGH data enters the latch and appears at the Q ...

Sample

High Speed CMOS Logic 8-Bit Addressable Latch

Sample

High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch

... is HIGH data enters the latch and appears at the Q ...