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Dual, 16-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices

Dual, 16-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter RSS Sample
  • Darmowa próbka
MPN:
AD9122
Producent:
ANALOG DEVICES
Dodany do bazy:
Ostatnio widziany:
Zmiana ceny:
-100% (21.01.2025)
Poprzednia cena:
44.30

The AD9122 is a dual 16-bit, high dynamic range, digital-to-analog converter (DAC) that provides a sample rate of 1230 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9122 comes in a 72-lead LFCSP.

The AD9122-EP supports defense and aerospace applications (AQEC).

Product Highlights

* Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies.

* A proprietary DAC output switching technique enhances dynamic performance.

* The current outputs are easily configured for various single-ended or differential circuit topologies.

* Flexible LVDS digital interface allows the standard 32-wire bus to be reduced to ½ or ¼ of the width.

Applications

* Wireless infrastructure

* W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE

* Digital high or low IF synthesis

* Transmit diversity

* Wideband communications: LMDS/MMDS, point-to-point

* Flexible LVDS interface allows word, byte, or nibble load

* Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF

* Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω

* Integrated 2×/4×/8× interpolator/complex modulator allows

carrier placement anywhere in the DAC bandwidth

* Gain, dc offset, and phase adjustment for sideband suppression

* Multiple chip synchronization interfaces

* High performance, low noise PLL clock multiplier

* Digital inverse sinc filter

* Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS, full operating conditions

* 72-lead, exposed paddle LFCSP

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