74AUP2G132DC,125

74AUP2G132DC,125 is a dual 2-input NAND gate with schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. It complies with JEDEC standards (JESD8-12 (0.8V to 1.3V), JESD8-11 (0.9V to 1.65V), JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V). It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V). It is used in applications such as wave and pulse shaper, astable multivibrator, monostable multivibrator.