10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter

The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.

The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.

Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

* High Performance—Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input.

* Low Power—Consumes only 410 mW @ 300 MSPS.

* Ease of Use—LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.

* Serial Port Control—Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation.

* Pin-Compatible Family—12-bit pin-compatible family offered as AD9230.

APPLICATIONS

* Wireless and wired broadband communications

* Cable reverse path

* Communications test equipment

* Radar and satellite subsystems

* Power amplifier linearization

* SNR = 60.1 dBFS @ fIN up to 70 MHz @

300 MSPS

* ENOB of 9.7 @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS)

* SFDR = −80 dBc @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS)

* Excellent linearity

DNL = ±0.1 LSB typical

INL = ±0.2 LSB typical

* LVDS at 300 MSPS (ANSI-644 levels)

* 700 MHz full power analog bandwidth