12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

The AD9613 is a dual 12-bit, analog-to-digital converter (ADC) with sampling speeds up to 250 MSPS. The AD9613 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The ADC output data are routed directly to the two external 12- bit LVDS output ports and formatted either as interleaved or channel multiplexed.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control are accomplished using a 3- wire SPI-compatible serial interface.

The AD9613 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

* Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.

* Fast overrange and threshold detect.

* Proprietary differential input maintains excellent SNR performance for input frequencies up to 400 MHz.

* SYNC input allows synchronization of multiple devices.

* 3-pin, 1.8V SPI port for register programming and register readback.

* Pin compatibility with the AD9643, allowing a simple migration up to 14 bits, and with the AD6649 and the AD6643.

Applications

* Communications

* Diversity radio systems

* Multimode digital receivers (3G)

* TD-SCDMA, WiMax, WCDMA,

CDMA2000, GSM, EDGE, LTE

* I/Q demodulation systems

* Smart antenna systems

* General-purpose software radios

* Ultrasound equipment

* Broadband data applications

* SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS

* SFDR = 86 dBc at 185 MHz fIN and 250 MSPS

* −149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS

* Total power consumption: 770 mW at 250 MSPS

* 1.8 V supply voltages

* LVDS (ANSI-644 levels) outputs

* Integer 1-to-8 input clock divider (625 MHz maximum input)

* Sample rates of up to 250 MSPS