Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs

The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz.

The AD9523-1 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.

The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO.

An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.

Applications

* LTE and multicarrier GSM base stations

* Wireless and broadband infrastructure

* Medical instrumentation

* Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

* Low jitter, low phase noise clock distribution

* Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols

* Forward error correction (G.710)

* High performance wireless transceivers

* ATE and high performance instrumentation

* Output frequency: <1 MHz to 1 GHz

* Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)

* Zero delay operation

* Input-to-output edge timing: <150 ps

* Dual VCO dividers

* 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS

* 14 dedicated output dividers with jitter-free adjustable delay

* Adjustable delay: 63 resolution steps of ½ period of VCO output divider

* Output-to-output skew: <50 ps

* Duty cycle correction for odd divider settings

* Automatic synchronization of all outputs on power-up

* Absolute output jitter: <150 fs at 122.88 MHz

* Integration range: 12 kHz to 20 MHz

* Broadband timing jitter: 124 fs

* Digital lock detect

* Nonvolatile EEPROM stores configuration settings