12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter

The AD9634 is a 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9634 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

The ADC output data are routed directly to the external 12-bit LVDS output port.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-wire, SPI-compatible serial interface.

The AD9634 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

* Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.

* Fast overrange and threshold detect.

* Proprietary differential input maintains excellent SNR performance for input frequencies up to 350 MHz.

* 3-pin, 1.8V SPI port for register programming and readback.

* Pin compatibility with the AD9642, allowing a simple migration up to 14 bits, and with the AD6672.

APPLICATIONS

* Communications

* Diversity radio systems

* Multimode digital receivers (3G)

TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE

* I/Q demodulation systems

* Smart antenna systems

* General-purpose software radios

* Ultrasound equipment

* Broadband data applications

* SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS

* SFDR = 87 dBc at 185 MHz AIN and 250 MSPS

* −150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS

* Total Power consumption: 360 @ 250 MSPS

* 1.8 V supply voltages

* LVDS (ANSI-644 levels) outputs

* Integer 1-to-8 input clock divider (625 MHz maximum input)